1. Field of the Invention
This invention relates to a semiconductor memory device, more specifically, to an error detection and correction system adaptable for use therein.
2. Description of the Related Art
Electrically rewritable and non-volatile semiconductor memory devises, i.e., flash memories, increase in error rate with increasing of the number of data rewrite operations. In particular, as a memory capacity increases and the miniaturization is enhanced, the error rate increases more. In this view point, it becomes a material technique to mount an ECC circuit on a flash memory chip.
There has been provided such a technique that an ECC circuit is formed on a flash memory chip or in a memory controller (for example, JP-A2000-173289).
To constitute a BCH-ECC system using Galois finite field GF(2n), in which 2-bit or more errors are correctable, if error location search is performed in such a way as to sequentially substitute finite field elements in the error searching equation to obtain elements satisfying the equation, it takes a very long operation time, and read/write performance of the memory will be largely reduced even if the system is formed as on-chip one.
Therefore, it is desired to constitute a high speed ECC system without the above-described sequential searching, which does not sacrifice the memory performance.